// E12Defines.v for hello_world_e12 sample

// This is a signal to MemoryPeripherals.v that we want it to include our ExtendedMemPeripherals.v
`define ENABLE_EXTENDED_MEM_PERIPHERALS 1

// Here we indicate which capabilities this image has.
`define IMAGE_CAPABILITIES    (`PICO_CAP_FLASH | `PICO_CAP_TURBOLOADER)

// The BaseE12Defines.v, included below, defaults to the LX version of the Virtex-4 chip.
//`define IS_E12FX
`define IS_E12LX


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  E12Defines.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Pico Computing, INC.                     ////
//// http://www.picocomputing.com                                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////////////////////////////////////////////////////////////////////JF


`ifndef VERSION

//-----------------------Version Info------------------------------------
`define VERSION_MAJOR                8'h03
`define VERSION_MINOR                8'h06
`define VERSION_RELEASE              8'h00
`ifndef VERSION_COUNTER	                  
 `define VERSION_COUNTER             8'h00
`endif
`define VERSION_UPPER_UPPER         `VERSION_MAJOR
`define VERSION_UPPER_LOWER         `VERSION_MINOR
`define VERSION_LOWER_UPPER         `VERSION_RELEASE
`define VERSION_LOWER_LOWER         `VERSION_COUNTER

//Card Selection: Default E12 LX  - Overide this in project-specific E12Defines.v
`ifndef IS_E12LX                                                     /*Define this for an LX25 FPGA*/
   `ifndef IS_E12FX                                                  /*Define this for an FX12 FPGA*/
      `define IS_E12LX                                               /*Default LX25 */
   `endif
`endif

`define VERSION CF RELEASE FEBRUARY 25, 2006

// Enable implied options
`ifdef INCLUDE_PPC
   `define INCLUDE_CPU
`endif
`ifdef INCLUDE_CPU
   `define ENABLE_RAM_PADS
   //`define ENABLE_GPIO_PADS // for the uart?
`endif
`ifdef ENABLE_GPIO
   `define ENABLE_GPIO_PADS
`endif

// default to no backplane
`ifndef BACKPLANE_REQUIRED
	`define BACKPLANE_REQUIRED 0
`endif


//-----------------------Optional Peripherals----------------------------
//`define DISABLE_TUPLE                                              /*This enables the configuration ROM (also known as a tuple)*/
`define ENABLE_CARD_INFO                                             /*This enables a module that holds the firmware version number and capabilities*/
//`define ENABLE_EXTENDED_MEM_PERIPHERALS                            /*This is used for the Impulse/C plugin and various crypto modules*/
//`define ENABLE_GPIO                                                /*General Purpose IO Interfaces*/


//-----------------------------Ethernet----------------------------------
`define MDIO_ADDRESS 26'h200000                       /*0x08000000*/ /*Ethernet Management Interface*/


//---------------------System Generator for DSP--------------------------
`define SYSGEN_BANK_ADDRESS 31'h70000000              /*0xE0000000*/ /*System Generator Bank Selection Address*/
`define SYSGEN_STEP_CLOCK_ADDRESS 31'h70000001        /*0xE0000002*/ /*System Generator Step Clock Address*/
`define SYSGEN_MIN_ADDRESS 30'h38000001               /*0xE0000004*/ /*System Generator Databus Start Address*/
`define SYSGEN_MAX_ADDRESS 30'h39000000               /*0xE4000003*/ /*System Generator Databus Max Address*/
`define SYSGEN_BASE_ADDRESS 32'h38000001              /*0xE0000004*/ /*System Generator Base Address*/
`define VFDCM_BASE_ADDRESS 24'hE50000                 /*0xE5000000*/ /*Variable Frequency DCM Base Address*/
`define VFDCM_STATUS_CONTROL_ADDRESS 31'h72800080     /*0xE5000100*/ /*Variable Frequency DCM Control/Status Address*/
`define VFDCM_RESET_PASSWORD 16'hD00F                                /*Variable Frequency DCM Reset Password*/
`define VFDCM_ENABLE_PASSWORD 16'hDA00                               /*Variable Frequency DCM Enable Password*/
`define VFDCM_CLEAR_PASSWORD 16'h0000                                /*Variable Frequency DCM Global Clear*/



//-------------------------General Purpose IO----------------------------
`define GPIO_SETUP 31'h7FFF8000                       /*0xFFFF0000*/ /*GPIO Setup Register [Word Addressing]*/
`define GPIO_RAW   31'h7FFF8001                       /*0xFFFF0002*/ /*GPIO Raw Interface [Word Addressing]*/

//------------------------IO Address Bus Width---------------------------
                                                                     /*The number of bytes accessable by the IO Address Bus is 2^(PCMCIA_ADD_LINES)*/
`define PCMCIA_ADR_LINES 8                                           /*Number of address lines*/
//------------------Tuple and Configuration Registers--------------------
`define COA1_ADDRESS 10'h100                          /*0x200*/      /*This is the base address for the configuration option registers as defined in the TPCC_RADR field of the configuration tuple [Word Addressing]*/
                                                                     /*Configuration option registers (COA) start here*/                                               


`define COA2_ADDRESS 10'h138                          /*0x270*/      /*This is the base address for the configuration option registers as defined in the TPCC_RADR field of the configuration tuple [Word Addressing]*/
                                                                     /*Configuration option registers (COA) start here*/
                                                      

//------------------Memory Address Extension Module----------------------
`define IO_ADDRESS_EXTENSION_1 `PCMCIA_ADR_LINES 'h02 /*0x004*/      /*Address Extension Register A[26:11] (Located in IO Space) [Word Addressing]*/
`define IO_ADDRESS_EXTENSION_2 `PCMCIA_ADR_LINES 'h03 /*0x006*/      /*Address Extension Register A[31:27] (Located in IO Space) [Word Addressing]*/

`define ATTRIB_ADDRESS_EXTENSION_1 10'h10B            /*0x216*/      /*Address Extension Register A[18:11] (Located in Attribute Memory) [8 Bit Even Accesses]*/
`define ATTRIB_ADDRESS_EXTENSION_2 10'h10C            /*0x218*/      /*Address Extension Register A[26:19] (Located in Attribute Memory) [8 Bit Even Accesses]*/
`define ATTRIB_ADDRESS_EXTENSION_3 10'h10D            /*0x21A*/      /*Address Extension Register A[31:27] (Located in Attribute Memory) [8 Bit Even Accesses]*/


//--------------------JTAG Parallel Port Emulator------------------------
`define LPT_DATA_ADDRESS 2'h0                         /*0x000*/      /*LPT IO Base Address         [Byte Addressing]*/
`define LPT_STATUS_ADDRESS 2'h1                       /*0x001*/      /*LPT IO Base Address + 1     [Byte Addressing]*/
`define LPT_CTRL_ADDRESS 2'h2                         /*0x002*/      /*LPT IO Base Address + 2     [Byte Addressing]*/

//-------------------------Status and Reset------------------------------
`define STATUS_ADDRESS `PCMCIA_ADR_LINES'h07          /*0x00E*/      /*Writing the FLASH_RESET_PASSWORD to this address does a hardware reset to the card [Word Addressing]*/
`define STATUS_FLASH_READY                            16'h1          /*Flash READY/BUISY Status*/
`define STATUS_DCMS_LOCKED                            16'h2          /*DCM Locked Snoop*/
`define STATUS_BACKPLANE_DETECTED                     16'h4          /*Backplane Detected or Not*/
`define PICOPORT_RESET_PPC  `STATUS_ADDRESS                          /*Give the reset port a more sensible name*/
`define FLASH_RESET_PASSWORD                          16'hDEAF       /*This is password to execute a flash rom reset*/
`define MAGIC_NUM_ADDR                                `PCMCIA_ADR_LINES 'h06 /*0x0C*/
`define PICO_MAGIC_NUM                                16'h5397

//-------------------CPLD Controller (TurboLoader)-----------------------
`define CPLD_CONTROLLER_RELOAD_PASSWORD 8'hAD                        /*CPLD Reload Password*/
`define CPLD_CONTROLLER_RELOAD_ADDRESS 10'h208        /*0x410*/      /*CPLD Reload Address [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_LLSB_ADDRESS 10'h20A /*0x414*/      /*CPLD Peekaboo LLSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_LMSB_ADDRESS 10'h20B /*0x416*/      /*CPLD Peekaboo LMSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_MLSB_ADDRESS 10'h20C /*0x418*/      /*CPLD Peekaboo LLSBs [Word Addressing]*/
`define CPLD_CONTROLLER_PEEKABOO_MMSB_ADDRESS 10'h20D /*0x41A*/      /*CPLD Peekaboo LMSBs [Word Addressing]*/


//--------------------------DCM Utilization------------------------------
//`define DISABLE_DCM1                                               /*Each DCM that is not used must be disabled*/
//`define DISABLE_DCM2                                               /*One DCM is used by the compact flash decoder*/
`define DISABLE_DCM3                                                 /*Commenting these out when a DCM is not in use voids warranty*/
`define DISABLE_DCM4                                   
`ifdef IS_E12LX                                                      /*There are only 4 DCMs on the E-12 EP*/
   `define DISABLE_DCM5
   `define DISABLE_DCM6
   `define DISABLE_DCM7
   `define DISABLE_DCM8                                              /*This should be the last DCM commented out*/
`endif


`endif

